1. Field of the Invention
The present invention relates to a display device and in particular to a driving apparatus for a display device having a power save mode and reduced power consumption.
2. Description of the Related Art
Flat panel display devices such as a liquid crystal and an organic EL display devices are generally thin, lightweight, and consume less power. Because of these characteristics, flat panel display devices are suited for use as display devices for portable devices, such as mobile phones, and have therefore come to be widely employed in many such portable devices.
FIG. 1 shows a structure of a liquid crystal display device used as a display device for a mobile phone. The liquid crystal display device comprises a liquid crystal display (LCD) panel 200 constructed by sealing liquid crystal between a pair of substrates, a driving circuit 101 for driving the LCD panel 200, and a power supply circuit 350 for supplying the required supply voltage to the driving circuit 101 and LCD panel 200.
The driving circuit 101 comprises a latch circuit 10 for latching supplied RGB digital data, a digital-to-analog (D/A) converter circuit 12 for converting the latched data to analog data, and an amplifier 14 for amplifying the converted analog data and supplying it to the liquid crystal display panel 200 as R, G, and B analog display data. The driving circuit 101 further comprises a timing controller (T/C) 22 and a CPU interface (I/F) circuit 20 for receiving an instruction from a CPU (not shown) and outputting a control signal in response to the instruction. The T/C 22 generates a timing signal suited to display on the liquid crystal display panel 200 based on timing signals such as a dot clock DOTCLK, horizontal synchronization signal Hsync, and vertical synchronization signal Vsync.
The power supply circuit 350 generates a plurality of supply voltages as necessary. The power supply circuit 350 supplies a supply voltage VDD1 of a low voltage to the latch circuit 10 for performing digital signal processing and which is constructed from a CMOS logical circuit suited for low voltage driving, a supply voltage VDD2 of a higher voltage to the D/A converter circuit 12 and amplifier 14, and a supply voltage VDD3 of an even higher voltage to the LCD panel 200.
FIGS. 2A and 2B show two structures of a related art power supply circuit for generating the voltage VDD2 of the plurality of voltages. FIG. 2A shows a switching regulator type power supply circuit 350 and FIG. 2B shows a charge pump type power supply circuit 350.
The switching regulator type power supply circuit 350 depicted in FIG. 2A comprises a boosting section 351 including a coil L1 and a diode D1 provided, in that order, between the input and output, an oscillation circuit 35s for oscillating a predetermined pulse signal, and a transistor Tr36 for receiving the pulse signal from the oscillation circuit 35s at its gate. The power supply circuit 350 boosts the input voltage VIN at the coil L1 and diode D1 by controlling the transistor Tr36 on and off using the pulse signal from the oscillation circuit 35s. The obtained boosted supply voltage VDD2 is then supplied to the liquid crystal driving circuit 101 as its operation power supply. The power supply circuit 350 further comprises voltage dividing resistive elements R37 and R38 between its output end and the ground. A comparator 36 compares the divided voltage between the resistive elements R37 and R38 with a reference voltage Vref, and outputs a comparison signal. By controlling the oscillation frequency of the oscillation circuit 35s based on the comparison signal corresponding to the output voltage VDD2 from the comparator 36, the overall circuit is controlled so that the output voltage VDD2 remains stable.
The charge pump type power supply circuit 350 depicted in FIG. 2B comprises two capacitors C1 and C2, capacitor switches SW1 through SW4 for switching the supply route of the input voltage to the capacitors, an oscillation circuit 35c for generating a pulse signal for controlling the switching of the switches SW1 through SW4, an AND gate 37, and a NAND gate 39.
The oscillation circuit 35c generates a pulse signal having, for example, a duty ratio of 1/2. The pulse signal is supplied to the switches SW1 and SW2 via the AND gate 37 and to the switches SW3 and SW4 via the NAND gate 39, so that the groups of switches SW1 and SW2 and SW3 and SW4 are alternately opened and closed.
When switches SW3 and SW4 are closed, the input voltage VIN is applied to the electrode of the capacitor C1 at the upper side of the drawing, the lower electrode becomes the ground (GND), and, thus, the capacitor C1 is charged. At the next timing, the switches SW3 and SW4 are opened and the switches SW1 and SW2 are closed. In this case, the input voltage VIN is applied to the lower electrode of the capacitor C1, the voltage at the upper electrode of the capacitor C1 is boosted to a voltage of twice the input voltage VIN, and the output voltage VDD2 having a voltage of twice the input voltage VIN is obtained at the output end provided between the upper electrodes of the capacitors C1 and C2.
There is a strong demand for reducing the power consumption in portable instruments such as mobile phones and, therefore, in the display devices for such instruments. In order to satisfy this demand, a power save mode, in which the device power supply is controlled to be turned off in order to reduce the power consumption, is commonly employed.
The display device depicted in FIG. 1 also includes such a power save mode. The I/F circuit 20 analyzes a power save control instruction transmitted from a CPU (not shown) and generates a power save control signal. The power save control signal is supplied to the power supply circuits 350 of FIGS. 2A and 2B and may be, for example, a signal having different levels during the normal operation and during the power save mode. Both power supply circuits 350 of FIGS. 2A and 2B have a structure in which the generation of the supply voltage VDD2 is suspended when the power save control signal becomes a level indicative of the power save mode. Although not shown, the power supply VDD3 is similarly controlled to be turned off and the supply of the power supply to the LCD panel 200 is also suspended.
The power supply circuit 350 depicted in FIG. 2A includes transistors Tr35, Tr37, and Tr38, resistive elements R35 and R36, and an inverter 38 to adapt the power save mode. The power save control signal is low (L level) during the normal operation mode and high (H level) during the power save mode.
During the normal operation mode, the oscillation circuit 35s receives a power save control signal of L level and performs oscillation operation. The transistor Tr37 is turned on and, subsequently, the transistor Tr35 provided at the input-to-output route is turned on. At this point, the transistor Tr38 connected between the output end of the power supply circuit 350 and the ground is controlled to be turned off. Thus, during the normal operation, the voltage VDD2 obtained by boosting the input voltage VIN at the boosting section 351 is output.
During the power save mode, the power save control signal becomes H level. The oscillation circuit 35s suspends its oscillation operation, the transistor Tr37 is turned off, the transistor Tr35 is controlled to be turned off, and, thus, the output from the boosting section 351 is shut out. Moreover, because the transistor Tr38 is turned on, the output end is connected to ground. The output of the power supply circuit 350 becomes 0V, that is, the power supply circuit 350 is controlled to be turned off.
The power supply circuit 350 depicted in FIG. 2B, on the other hand, receives a power save control signal of H level during the normal operation and of L level during the power save mode, and generates a pulse signal when the power save control signal is at the normal H level. As a result, the groups of switches SW1 and SW2, and SW3 and SW4 are alternately controlled to be switched, the charge pump is enabled, and an output voltage VDD2 having a higher voltage than the input voltage VIN can be obtained. During the power save mode, on the other hand, when the power save control signal becomes L level, the oscillation circuit 35c stops its operation, the output of the AND gate 37 is fixed at L level, and the output of the NAND gate 39 is fixed at H level. Because of this, the capacitors C1 and C2 are discharged, output voltage is reduced, and, thus, the power supply circuit 350 is controlled to be turned off.
As described above, in the related art power supply circuits comprising a power save mode, the power consumption at the driving circuit 101 and at the LCD panel 200 is shut down in order to reduce the power consumption as a display device by controlling the power supply supplied to the driving circuit 101 and LCD panel 200 of the display device to be turned off during the power save mode.
However, when the power supply circuit is controlled to be turned off during the power save mode, the display device will be unable to display. In a mobile phone, for example, when the power save mode is activated, because the display power supply is controlled to be turned off, information such as the time of day indicated by the internal clock and radio wave conditions cannot be shown.
According to another related method, in order to enable display even during the power save mode, rather than the display power being switched off, the driving frequency of the display device is reduced. However, in a display device, unlike in a CPU, a reduction in the driving frequency not only reduces the operation speed but will also significantly affect the display quality. When the frequency becomes lower than a certain frequency, display flicker is produced, resulting in a significant degradation of the display quality. Therefore, there is a limit to how much power can be saved by reducing the driving frequency and therefore this method is not effective in reducing the power consumption.
Also, although the power consumption can be reduced by reducing the driving frequency in a digital processing circuit such as, for example, a latch circuit, where power is consumed when the signal is changed from H to L or from L to H, the power consumption cannot be reduced in an analog processing circuit such as a D/A converter circuit, an amplifier, or the like because the power consumption is for the most part independent of the driving frequency. Thus, reduction in the driving frequency is not by itself an effective means for reducing power consumption.
moreover, in order to enable display at a lower than normal reducible driving frequency, the design of the element structure within the LCD panel and the liquid crystal material or the LCD driving method must be change. As a result, a large design change is required, which can greatly add to the cost of the resulting display device.